1. Technical Field
The embodiments described herein relate to a semiconductor memory apparatus and more particularly, to a domain crossing circuit of a semiconductor memory apparatus.
2. Related Art
Generally, a synchronous semiconductor memory apparatus operates in synchronization with a clock signal. In this case, command signals or data that have been synchronized with an external clock signal, must be synchronized with an internal clock signal to operate in an internal circuit. In addition, internal clock signals, which have been synchronized with the internal clock signal, must be synchronized with an external clock signal, called “domain crossing” that refers to a domain change between an internal clock domain and an external clock domain.
FIG. 1 is a schematic block diagram of a conventional crossing circuit of a semiconductor memory apparatus. In FIG. 1, the domain crossing circuit includes a first counter 10, a replica 20, a second counter 30, a data input unit 40, a latch unit 50, and a comparator 60.
In FIG. 1, the domain crossing circuit converts a domain of an external clock signal ‘CLK_C’ into a domain of an internal clock signal ‘CLK_B’. Here, instead of the external clock signal ‘CLK_C’, the internal clock signal ‘CLK_B’ generated from a DLL circuit unit (not shown) is used as a reference clock signal serving as a reference for the output of an input data signal ‘IN’, and an output data signal ‘OUT’ is provided when a predetermined latency is satisfied. Accordingly, the domain crossing circuit constantly maintains arithmetic differences between count bits output from the first and second counters 10 and 20 to realize latency.
For example, the first counter 10 receives an initial value S<0:n> and consecutively counts from the initial value S<0:n> for every rising edge of the internal clock signal ‘CLK_A’ to output a first count signal ‘CNT_A<0:n>’ having (n+1) bits. The internal clock signal ‘CLK_A’ passes through the replica 20 to be the internal clock signal ‘CLK_B’ delayed by predetermined time. Accordingly, the second counter 30 is triggered by a reset signal ‘RESET’ for every rising edge of the internal clock signal ‘CLK_B’ to consecutively count so that a second count signal ‘CNT_B<0:n>’ having (n+1) bits is output. In this case, the internal clock signal ‘CLK_A’ and the internal clock signal ‘CLK_B’ are generated from the DLL circuit unit (not shown). The replica 20 is designed by taking account into delay time such that the phase of the internal clock signal ‘CLK_B’ is identical to the phase of the external clock signal ‘CLK_C’. Here, the replica 20 delays the internal clock signal ‘CLK_A’ by predetermined time so that the phase of the internal clock signal ‘CLK_B’ is identical to the phase of the external clock signal ‘CLK_C.’
In FIG. 1, the first counter 10 and the second counter 30 count bit signals while maintaining a predetermined clock interval such that the clock interval is equal to latency to be defined later. Here, the first and second counters 10 and 30 are 3-bit counters, wherein the first counter 10 counts from the initial value S<0:n>. For example, if the initial value S<0:n> is ‘100’, then the first counter 10 consecutively counts from ‘100’. Meanwhile, the second counter 20 always counts from ‘000’ after the reset signal ‘RESET’ is received. Accordingly, arithmetic differences in output bits of the two counters 10 and 30 are constantly maintained after the reset signal ‘RESET’ is activated, so that the latency of a semiconductor memory apparatus can be realized. In this case, the initial value S<0:n> of the first counter 10 may have various values according to latency required in the semiconductor memory apparatus.
The data input unit 40 receives an input data signal ‘IN’ to output a latch signal ‘LATCH’ in synchronization with the external clock signal ‘CLK_C’. In addition, the latch unit 50 triggers and latches the second count signal ‘CNT_B<0:n>’ at a rising edge of the latch signal ‘LATCH’. Such an operation of the latch unit 50 can be performed using a D flip-flop triggered at a rising edge of a signal. Accordingly, when a comparative enable signal ‘CMP_EN’ is activated, the comparator 60 compares a latch count signal ‘LATCH_B<0:n>’ having been latched in the latch unit 50 with the first count signal ‘CNT_A<0:n>’. If the latch count signal ‘LATCH_B<0:n>’ is equal to the first count signal ‘CNT_A<0:n>’, then the output data signal ‘OUT’ having a high level is applied.
For example, the latch count signal ‘LATCH_B<0:n>’ is triggered at the rising edge of the latch signal ‘LATCH’ and continuously latched without change, and the first count signal ‘CNT_A<0:n>’ is continuously counted. Accordingly, timing, in which the latch count signal ‘LATCH_B<0:n>’ is equal to the first count signal ‘CNT_A<0:n>,’ corresponds to latency information required in the semiconductor memory apparatus. Thus, the output data signal ‘OUT’ can be provided after predetermined latency from the input data signal ‘IN’.
In this case, the replica 20 is a chain of a plurality of inverters connected to each other in series. Accordingly, if an abnormal pulse occurs in the internal clock signal ‘CLK_A’ then the first counter 10 performs a count operation in response to an instantaneous pulse. However, if the internal clock signal ‘CLK_A’ having the abnormal pulse is applied to the replica 20, an RC component of the inverter chain serves as a low pass filter (LPF) to reduce the noise of voltage. Accordingly, the second counter 20 does not detect the abnormal signal.
The first counter 10 and the second counter 20 perform a count operation adjustably for desired latency while maintaining the same clock interval as described above. However, difference corresponding to one clock interval 1tCLK is made in the count number of the first and second counters 10 and 20 due to the application of the abnormal pulse signal. Accordingly, even if latch and comparative operations are performed thereafter, differences from the desired latency may occur.